I have a little question on a make file, here is the code:

KERNEL_VERSION := $(shell uname -r)
KERNEL_SOURCES := $(shell test -d $(KERNEL_MODLIB)/source && echo $(KERNEL_MODLIB)/source || echo $(KERNEL_MODLIB)/build)
obj-m   := main.o
PWD := $(shell pwd)
     $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules 
     $(RM) main.ko.unsigned  main.mod.c  main.mod.o  main.o modules.order  module.symvers .main* .tmp_versions/*

I want to know what does this code do:

$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules 

thx for advance~~


The command changes to the directory $(KDIR) and runs make from there to build the target modules.

$(MAKE) is a macro which runs the make executable. The reason for it (instead of just using make) is that that executable could have different names.

-C <directory> changes to a certain directory before running make.

SUBDIRS=<variable> defines the variable SUBDIRS when running make.

modules means it will try to build that target.

  • thx, but where will it put the target "module" built, in the $(KDIR) or in SUBDIRS? – Cong Li Oct 13 '15 at 15:06
  • It depends on that makefile - "modules" might not actually be a filename. – MasterOfBinary Oct 13 '15 at 15:10
  • indeed i found KBUILD_EXTMOD ?= $(SUBDIRS) and the definition of modules in the $KDIR makefile. Thx for the quick answer~ – Cong Li Oct 13 '15 at 15:19

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