What are the commands necessary to clear the L1, L2 and L3 cache in ubuntu?

Can this be done utilising the shell or do I need a higher level language?

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    Why do you need this? – muru Oct 4 '18 at 0:42
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    There shouldn't be any reason for you to have to manually manipulate your CPU caches, and for the most part you wouldn't see those caches anyways (they're part of the CPU architecture and operate transparent to the system). Why do you need to manipulate the caches? – Thomas Ward Oct 4 '18 at 0:53
  • You could call it a "science experiment". I have an attacker listening to the data on my L1 cache and I would like it to be obfuscated. I could work round the fact it buffers if anyone knows of a way. – user797940 Oct 7 '18 at 23:47

From: Way to flush/ clear the RAM and cache memories

It is not possible to do this with complete effectiveness at user level. Performance counters in the uncore can be used to derive the mapping of physical addresses to L3 slices (CBos) for any address range that the user can allocate and test, but that only tells you which CBo is being used, not which congruence class within that slice is being used. The size of the L3 slices suggests a straightforward mapping, but I don't know of any demonstrations that confirm the internal mapping.

At the gross level, on Xeon E5 v3 systems, reading an array that is 4x larger than the L3 cache size will clear nearly 100% of the prior data from the L1, L2, and L3 caches. This only requires process binding (e.g., "taskset" or "numactl --physcpubind" on Linux systems).


L1, L2 and L3 cache are terms used to describe caches used internally by the CPU and chipset. They are transparent to the system, that is, the existence or not of data in the caches shall never have any observable side effects on program execution or the data returned by any operation. There is therefore also no way to clear them and if there were, doing so would have no observable effect.

These caches are integral to the functioning of the CPU. Their contents are refreshed possibly millions of times per second, depending on the operations in progress.

  • Any "observable" side effects, which is why I need to flush them. – user797940 Oct 7 '18 at 23:47
  • Sorry if anything wasn't clear, I meant there are NOT any observable side effects. There is no way for data in the cache to be wrong or out of date. – thomasrutter Oct 8 '18 at 2:59
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    Ah I see, you are referring to a hypothetical situation in which they are observable – thomasrutter Oct 8 '18 at 3:11
  • Yes. Its my understanding that the virus that hit the Intel Industry, spectre meltdown, can be applied in a way that the speculative bypass allows confidential information such as login information and passwords to be leaked through the caches in the CPU, similar to its effects on RAM. – user797940 Oct 8 '18 at 4:51
  • This means that even when mitigating any vulnerabilities in the memory its self, the bug on an infected machine may live on in a live fashion within the caches in the CPU. – user797940 Oct 8 '18 at 4:51

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