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I'm wondering if there's a way to make one rule out of the following several rules which are all similar in a Makefile that I have to edit:

    @echo ........... Compiling $<
    $(CC) -c -o $@ $< $(OBJECT_CFLAGS)
    @echo ........... Compiling $<
    $(CC) -c -o $@ $< $(PROPERTIES_CFLAGS)
    @echo ........... Compiling $<
    $(CC) -c -o $@ $< $(WRAPPER_CFLAGS)
    @echo ........... Compiling $<
    $(CC) -c -o $@ $< $(SOCKET_CFLAGS)

Notice, aside from the variable name, the rule is exactly the same. Is there a nifty makefile trick I can use here?

FYI, *.d are themselves makefiles that are generated by g++ and describe the dependency of a cpp file.


share|improve this question
Sorry about that, Makefile commands seem to screw up formatting, can someone help me out here? – Bitdiot Oct 18 '12 at 19:21
Okay, thanks whoever did that!! – Bitdiot Oct 18 '12 at 19:26

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